VLSI design of an ATM switch with automatic fault detection

This paper describes a VLSI implementation of a multistage self-routing ATM switch fabric. The size of the switch prototype is 16/spl times/16 and is designed to handle the OC-12 (622 Mbps) link rate. Based on a bit-slice architecture, the entire 16/spl times/16 switch is implemented using four identical chips. The switch has multiple paths, created by a randomizer in front of the routing stages, between each input-output pair. The switch uses an input/output-buffering scheme and contains no buffers inside the fabric. To facilitate fault detection and isolation, we add automatic fault detection schemes at the node, chip, and system levels of the design.