RAISE: a detailed routing algorithm for SRAM based field-programmable gate arrays using multiplexed switches

This paper describes a new detailed routing algorithm, specially designed for those architectures that are found in most recent generations of Field-Programmable Gate Arrays (FPGAs). The algorithm also brings a solution for those architectures where multiplexed switches are used in order to decrease the chip area like the recently proposed FIPSOC FPGA. The algorithm, called RAISE, can be applied to a broad range of optimization problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels, with or without the use of multiplexed switches. RAISE (Router using Adaptive Simulated Evolution) searches not just for a possible solution, but tries to find the one with minimum delay. Excellent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.