Five Approaches to Deal With Problem of DC Offset in Phase-Locked Loop Algorithms: Design Considerations and Performance Evaluations

The presence of the dc component in the phase-locked loop (PLL) input results in fundamental frequency oscillations in the phase and frequency estimated by the PLL. The removal of these oscillations is a challenging task because of their low frequency. The aim of this paper is to provide a detailed analysis of several approaches that little work has been conducted on their application for addressing the problem of dc offset in the PLL algorithms. These approaches include using the dq-frame delayed signal cancellation (DSC) operator and the notch filter (NF) as the PLL in-loop filtering stages, and using the $\alpha \beta$ -frame DSC operator, the complex coefficient filter, and a cross-feedback network for blocking the dc offset before the PLL input. Design aspects of these methods are presented, some methods to enhance their performances are proposed, and their advantages and disadvantages are evaluated.