An efficient method for testing of L1 cache module in tiled CMPs architecture at low cost

A cost effective test structure to check a correctness of cache performance in chip multiprocessors (CMPs) is developed in this work. The basis of the work has been the cellular automata (CA) structure proposed by von Neumann in 1950's. The theory of 1-dimentional 3-neighborhood null boundary CA is developed to monitor the behavior of each of the processors cache in CMPs. The special class of single length cycle attractor cellular automata accepts the (March) read/write status of cache word/line and evaluates to decide on the inaccurate functioning of a cache module. In this way, the inability of the classical design to identify defective behavior of CMPs cache is overcome. The design further enables identification of the region of defective cache module in the CMPs.