Performance analysis of various scheduling algorithms using FPGA platforms

This paper discusses the synthesis and implementation of various scheduling algorithms for Network-on-Chip communication. Traditionally these scheduling algorithms were implemented on ASIC platforms generally for shared bus based interconnection systems. In this paper we carry a comparative analysis by synthesizing and implementing various scheduling algorithms for configuring the crossbar in input queued switches. The implementation is carried out using various arbitration networks responsible for scheduling 8-bit input requests. The implementation targets Spartan6 FPGA family. The analysis concludes that the scheduling algorithm based on CLA based encoding network shows lower power delay product and lower area delay product and a reasonably lower resource utilization when implemented for speed optimization goal.