Fused modulo 2n − 1 add-multiply unit

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Targeting to increase performance, in this work, we focus on optimizing the design of the modulo 2ⁿ - 1 Add-Multiply (AM) operation. We incorporate in the design the direct recoding of the sum of two numbers in its Modified Booth (MB) form. Compared to the conventional design of first instantiating a modulo 2ⁿ - 1 adder and then, driving its output to a modulo 2ⁿ - 1 multiplier, the proposed fused AM design yields considerable reductions in terms of critical delay, area complexity and power consumption.