Improving performance and reliability of 3D wafer level packaging with unique photoresist coating process

The increasing adoption of advanced wafer-level packaging (WLP) technologies and high-density interposer concepts clearly reflects the permanent need for form factor reduction, Summary form only given: Smaller process geometries and higher-count I/O on ICs. Currently, several strategies are being pursued to achieve these goals. The most promising approaches are summarized under the concept of three-dimensional integrated circuits (3D-IC) and three-dimensional wafer level packaging (3D-WLP) technology. The transition from two-dimensional (2D) packaging to more advance 3D packaging is considered to be one of the major developments in the semiconductor industry.A key component for 3D device integration schemes is the requirement of vertical through-silicon-via (TSV) interconnections that enables electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias. Despite the potential benefits associated with the incorporation of TSVs, significant challenges have to be overcome. Among these is: (1) the containment of electrical losses in TSVs due to insertion loss and crosstalk; and (2) attaining lasting reliability of the TSV interconnects, which is truly challenged by thermal induced stress caused by the co-efficient of thermal expansion (CTE) mismatch between the interconnect metal and the silicon substrate. This thermal induced stress can be sufficient to permanently degrade device performance, induce mechanical failure caused by cohesive cracking in the silicon, and cause delamination between the TSV and the silicon matrix. Ultimately, thermal induced stress can cause TSVs to pop-up from the silicon wafer and damage Back-End-Of-Line (BEOL) structures permanently. Accordingly, the incorporation of TSVs has to be carefully designed to inhibit parasitic effects on the 3D stack caused by thermo-mechanical reliability issues To alleviate these issues, the authors of this article will demonstrate a novel technique for applying photoresist and other functional polymers at and within TSV geometries. The authors will show how this technique can create passivation layers that not only protect against corrosion, but also enable isolation to reduce electrical noise, as well as create compliant layers to mitigate thermal stress. The resulting benefits of improved TSV interconnect designs will ultimately pave the way for broad utilization of 3D-WLP concepts with high bandwidth communication between chips at lower power consumption and dense metallization with reduced electrical losses.