Low power approach for implementation of 8B/10B encoder and 10B/8B decoder used for high speed communication

In this paper a clock gated 8B/10B encoder and 10B/8B decoder circuit is implemented. In this we design the encoder decoder circuit with gated clock as it optimized the power without degrading the performance of the circuits. The technology used in this paper is gated clock circuit using negative latch. This gated clock then used to control the encoder and decoder circuit. The RTL view of encoder and decoder with clock gating are shown in Figures 13 and 14. Encoder without clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.10 mW and 111 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 1.05 mW and 149 mW respectively. Encoder with clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.05 mW and 108 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 0.47 mW and 113 mW respectively. Decoder without clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.05 mW and 108 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 0.49 mW and 116 mW respectively. Decoder with clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.05 mW and 108 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 0.49 mW and 113 mW respectively. The encoder and decoder circuits are design using verilog HDL and are simulated in ModelSim 10.3c. For the RTL view and power report of the implemented circuit we used Xilinx ISE suite 13.4.