Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools

Next generation radar systems require that massive computations be performed in real time and have size, weight and power restrictions. Increasingly, cost is also playing a major role. This paper introduces two major innovations that help meet these SWaP-C requirements. The first innovation is the COTS OpenVPX board from Curtiss-Wright called CHAMP-FX4 that contains three large Virtex 7 FPGAs with a total of 10,800 DSP Slices and 4,410 on-chip Block RAMs. The second innovation is Concurrent EDA's FPGA design automation tools that analyze and synthesize C/C++ into high-performance FPGA firmware. This paper describes how SAR processing was accelerated by 39 to 46 times faster than a single core of an Intel Core i7 CPU running at 3.6GHz and consumed less than half of one FPGA, 1/6^th of the available FPGA area on Curtiss-Wright's CHAMP-FX4 hardware. Total design-time was 6 weeks.