A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock

In this paper, we aim to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6 /spl mu/m SPDM CMOS process. The simulation shows that this chip can operate in the range between 60 MHz and 400 MHz, and operates at 4/spl times/ the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1 ns. The IC consists of 4026 MOS transistors and the core size of the chip layout is 923 /spl mu/m/spl times/921 /spl mu/m.