Phase-jitter dynamics of second-order digital phase-locked loops

Recent studies of digital phase-locked loops by Gardner have shown that an unwanted phase 'jitter' occurs in such systems, due to frequency quantisation in a number-controlled oscillator. In a previous paper, we used techniques from the theory of nonlinear dynamics to verify Gardner's empirical results and to illuminate the behaviour of first- and second-order loops. In this paper we shall expand on that work; in particular, we shall consider both the transient and steady-state dynamic behaviour of the second-order DPLL and describe the motion of steady-state trajectories when the input frequency is rational.