Fault tolerant adaptive XY routing for HPC mesh

With each nanometer technology, transistor size is shrinking and computation speed is increasing. Computation speed is bounded by the power consumption of cores and connecting network. So peak network power can not go beyond a certain limit since it starts aging due to thermal effect. Therefore, power optimization and fault handling become an important issue of on chip networks. In this paper we have addressed such issues via Homogeneous Parallel Concentrated (HPC) mesh topology and proposed an adaptive XY routing. It provides performance (in terms of throughput and latency) while having less power consumption and can handle up to 3 subnetwork failure by using adaptive fault tolerance routing. We have compared HPC mesh performance power and area with mesh topology and results show the effectiveness of this approach.