VIPPE, parallel simulation and performance analysis of multi-core embedded systems on multi-core platforms

Verifying the correctness of multi-processing embedded systems is a complex task and in addition to that system-on-Chips (SoC) are integrating a continuously growing number of cores. Native simulation technologies have been proposed to generate virtual platforms at the beginning of the design process, reducing porting efforts. As with any Discrete-Event simulation technique, native simulation causes problems when trying to take advantage of the multi-processing capabilities of current host workstations where the simulation will be executed. Several concurrent simulated threads can be run in parallel in the host, however, ensuring deterministic behavior requires synchronizing all of them periodically in order to maintain causality among events. As a consequence, the number of cores that can be active during simulation is dramatically reduced. This paper proposes a native simulation framework, called VIPPE, which makes an efficient use of the multi-core host platform. The approach has been evaluated with a benchmark of the PARSEC suite and the results show that the simulation speed-up (with the number of target threads) is close to the original application speed up. This demonstrates the limited impact on performances of the proposed simulation parallelization methodology.