Mitigating voltage droop during scan with variable shift frequency

This paper describes an innovative approach for executing scan patterns on the tester that significantly reduces peak voltage droop during scan shift by stepping up the shift frequency during the beginning of each scan load/unload procedure. A methodology is presented to tune one or more frequency steps to achieve the largest reduction in voltage droop. Using this approach, higher target shift frequencies can be achieved which directly reduce test time and cost. Results are presented from the GPU of a 32-nm APU to which variable shift patterns were applied to achieve a 23.3% test time reduction in high volume production.