Design and simulation of a wideband channelized transceiver for DRFM applications

This paper proposes an architecture for system-on-chip (SOC) implementation of wideband channelized transceiver for DRFM application. Deterministic pulse radar signal detection with unknown parameters, wideband frequency coverage and high instantaneous bandwidth requirement render the design and implementation of such wideband radar jamming systems difficult. Also, low power requirement and area constraints result in challenging design of integrated circuit for such applications. The proposed architecture uses channelized transceiver architecture with subbands along with discrete time signal processing to process pulse radar signals with continuous frequency coverage from 1 GHz to 20 GHz and instantaneous bandwidth up to 300 MHz. Also, non-parametric power spectral density estimation is used to detect incoming radar pulse in noisy environment. The overall system architecture is implemented and co-simulated using Cadence Spectre Verilog-AMS and Simulink-Matlab Models. Performance results show an input dynamic range of 40 dB (−60 dBm to −20 dBm) with receiver noise figure as low as 4 dB. Also, the worst case acquisition time of 20 pulse repetition intervals is achieved.