Area and power analysis of AES using hardware and software Co-design

This paper investigate the analysis of power and area of Advanced Encryption Standard (AES) algorithm using different design tool like ARM based, Hardware (VHDL/Verilog) and HW/SW. Results of area and power consumption for different design are varying and the percentage improvement in the power and area is marginable.The power improvement range is between 22.5% to 90% and the area improvement range is between 5% to 30%. The proposed AES is implemented on different hardware like ARM, microblaze processor and FPGA.