Performance assessment of ULP analog/RF MOSFET architectures

Ultra low power (ULP) operation is increasingly in demand for future System-on-Chip (SOC) circuits using nanoscale analog/RF transistors. In this work, we analyze the analog/RF performance metrics of different ULP MOSFET architectures and quantify the advantages and challenges associated with underlap inversion-mode (INV), Junctionless (JL), lateral tunnel FET (LTFET) and vertical tunnel FET (VTFET) in terms of gain and bandwidth.