An improvement of SOA on n-channel SOI LDMOS transistors

A new n-channel SOI LDMOS transistor which has an n/sup +/ drain structure with a buffer layer is proposed. The electric field of n/sup +/ drain region can be reduced by 68% in this structure compared with conventional LDMOSFETs. The generation of hole current, which turns on a parasitic bipolar transistor and causes the second breakdown, can be suppressed. This device was fabricated in the 0.8 /spl mu/m CMOS process on a SOI wafer and the buffer layer doping concentration was optimized by simulations. From the measurement results, it was confirmed that the second breakdown voltage at V/sub gs/=20 V was improved from 35 V to 80 V in the proposed structure. Also, this device has a breakdown voltage of 240 V and a specific on-resistance of 16.9 m/spl Omega//spl middot/cm/sup 2/, which is the best reported performance for this voltage range.