A novel trench formation and planarization technique using positive etching and CMP for smart power ICs

A new trench isolation technique has been demonstrated which can be used to make high voltage integrated circuits with trench isolation. The technique consists of positive etching using HBr and SiF/sub 4/ chemistries with 45% He-O/sub 2/ additives and global planarization after trench refill techniques using chemical-mechanical polishing (CMP). The novel technique provides better surface quality of 3.1 /spl Aring/ RMS roughness as measured by AFM, better CMP uniformity of less than 3%, and better leakage characteristics of less than 1 nA at 400 V.