Analysis of power losses in MOSFET synchronous rectifiers by using their design parameters

Power losses in MOSFET synchronous rectifiers are discussed. A simple analytical model which is physical and uses only the design parameters has been developed for analysis of capacitive losses in the vertical MOSFET. A criterion is proposed to evaluate the performance of MOSFET synchronous rectifiers with regard to power loss. By using the model and the criterion, the influences of scaling geometry and trench gate structure on the power losses are analyzed. The results show that, contrary to the conduction loss, the capacitive loss in the UMOSFET increases with scaling geometry. Fractional analysis of the power loss reveals that for the UMOSFET with lower blocking voltages, the reduction in power loss is limited by the capacitive loss instead of the conduction loss calculated from the ideal silicon limit.