Scaling issues in lateral power MOSFETs

The interconnect limitations and scaling issues for large area lateral multi-cell power MOS transistors as they approach the ULSI realm are investigated. The increased importance of scaling the metal pitch and the number of layers for different MOS technologies is discussed. Furthermore, the voltage drop and current distribution along metal runners for different examples of layout options are examined in order to gain insight into scaling and layout considerations. It is shown that the temperature behaviour of devices with different metal lengths can be used to extract the contribution of the metal interconnects from measured data.