An ultra low-voltage standard cell library in 65-nm CMOS process technology

In this paper, the design of an ultra-low voltage standard cell library is discussed. This includes the design constraints in designing each gate on a schematic level as well as techniques used in designing the layout. The method of performing timing and power characterization of the standard cell library and how the logical and physical library files are generated are discussed. The accuracy of the standard cell library is then verified through the use of several test circuits.