A 1-G sample/S 71-dB SFDR CMOS S/H circuit

This paper presents a 1-Gsample/s sample and hold (S/H) circuit based on a source follower in a 40 nm SMIC CMOS process. Under the conception of modulating the bias current of source follower, a kind of technique is adopted to cancel its body effect and channel length modulation. This S/H achieves over 70dB spurious free dynamic range (SFDR) for a sine wave input with 402.3MHz and 1.6V_ppd at 1GHz sampling frequency, 7dB more than the conventional structure. This S/H dissipates 17mW from a 2.5V supply.