Finfet and gate-all-around device design and performance/yield optimization

The three-dimensional (3D) nature of Fin-, Nanowire-, or Gata-All-Around-FETs raises a host of unique challenges to device design and optimization. The sensitivity of a FinFET's threshold voltage (Vth) to the Vth-implant is much lower than in a planar FET but can be improved by 5× through a change in the integration flow (“Well-Implant-Before-STI-Recess”). There still is a Halo implant in a FinFET that is analogous to the Halo implant in planar devices used for device-performance tuning. Unique to FinFETs is a 2nd “Halo” implant, which is effective for Vth adjustment. A Source-Drain-Extension (SDE) implant is instrumental for control of recess-spacer/recess-etch variability.