High resistivity SOI wafer for mainstream RF System-on-Chip

Systems-on-Chip (SoC) and Systems-in-Package (SiP) are the most feasible solutions to fulfil the requirements of the new communication systems [1]. Both solutions will lead to a fundamental change in the design of analogue front-end architectures. It requires a high performance technology with devices that provide complex digital functionalities and can easily achieve operating frequencies in the GHz range. Therefore, it appears that only the best submicron CMOS technologies could provide a feasible and cost-effective integration of the communication systems. SOI MOSFET technology has demonstrated its potentialities for high frequency reaching cut-off frequencies close to 500 GHz for nMOSFETs [2] and for harsh environments (high temperature, radiations). Partially depleted (PD) SOI is now massively serving the 45-nm digital market where it is seen as a low-cost - low-power alternative to bulk Si. Fully depleted (FD) devices are also widely spread as they outperform existing semiconductor technologies for extremely low power analogue applications [3]. For RF and SoC applications, SOI also presents the major advantage of providing high resistivity (HR) substrate capabilities, leading to substantially reduced substrate losses. Substrate resistivity values higher than 1 kΩ-cm can easily be achieved and High Resistivity Silicon (HR-Si) is commonly foreseen as a promising substrate for radio frequency integrated circuits (RFIC) and mixed signal applications [4].