High performance analysis of a CORDIC architectures based on FPGA: A comparative approach

The CORDIC is basically used to evaluate different elementary function. Volder has introduced a CORDIC algorithm technique for evaluation of trignometric operation as well for binary complex methods. By using basic Volders CORDIC algorithm and using two modes of operation such as ROTATION and VECTORING operation in which the number of word times per operation is equal to the word length. In this paper, the novel ideas is to design and implementation of the CORDIC algorithm based architectures specific to FPGA devices. The algorithm is implemented for serial as well as parallel CORDIC architecture. The real data type input values are considered to get the simulation output but very difficult to synthesize on FPGA base device. The analysis is done for the parameters such as area speed, latency, throughput output and finally power. To check the functionality of the algorithm the design has been simulated for different value of sine and cosine. The simulation is carried out using Xilinx ISim 13.1 and power matrices are obtain using Xilinx Xpower Analyzer tool.