A Developing Method for Parallel Program Based on System Generator

FPGA is fit for large parallel programs. To improve the performance of EULER3D program, a PC+FPGA solution based on system generator was practiced. Based on the analysis of the algorithm's hotspot, a system model was built for EULER3D kernel algorithm constructed with system generator blocks. The data exchange between the PC and the FPGA board used the Gigabit Ethernet MAC interface, and the overall performance of the software improves a lot. The above method was compared to the manual HDL coding development method. The result shows that, with the help of system generator, it can reduce the development cycle and improve the efficiency.