Low power cascaded folding signal conversion

Folding of analog signals is one of the most efficient techniques employed in digitization of high speed signals at intermediate resolution. However, its implementation is restricted by distortion resulting from limited bandwidth at the output of the folders, interpolation at the output and comparator offset. In this paper a method to increase input signal processing capabilities and reduce the number of required comparators based on cascaded folding of analog signals is reported. The proposed method is evaluated on a prototype A/D converter fabricated in standard single poly, six metal 180-nm CMOS.