High-speed and low-cost reverse converters for the (2n-1, 2n, 2n+1) moduli set

In this brief, new architectures are presented for the conversion of residues to binary equivalents in the (2n-1, 2n, 2n+1) moduli set. Both of the architectures presented are based on a new algorithm, which eliminates a multiplication. In the design of the architectures, speed and cost are considered as the principal factors. The proposed architectures use fewer multipliers and adders of smaller size. A comparison in terms of hardware requirements, delay estimates, and complexity is made to establish the advantages of the proposed design.