Energy efficient implementation, power aware simulation and verification of 16-bit ALU using unified power format standards

With the increase in the demand for high performance and high speed VLSI systems such as network processors in networking or SOCs in communication and computing has shifted the focus from traditional performance parameters towards the analysis of power consumption. The power budget and management among the domains of a system is of real concern. Hence, the power aware design using clock gating, power gating, dynamic voltage scaling and frequency scaling are the most used design techniques. Employing such low power techniques at the RTL creates new design and verification challenges. The challenges are: how can one domain be power downed, how can it be put back to power up state and do they retain or restore the previously computed data and still function correctly. These can be answered and implemented using new methods of implementation and verification using the unified power format (UPF)standards for low power intent designs. This paper presents the work carried out in applying the metioned techniques to the 16-bit ALU functional blocks. The paper discusses the power aware verification flow, power intent using UPF and managing the power among the domains or the functional blocks in a low power design. The implementation of this advanced RTL simulation and verification technique is carried out using QuestaSim Power Aware Verification tool. Simulation results efficiently prove the validation of the applied UPF standards in designing the 16-bit ALU.