Comparative analysis of various Domino logic circuits for better performance

In this paper, basically the delay and the noise margin parameter associated in the circuit has been analyzed. The paper gives a better approach for the reduction in delay variation and compares the result with different-different types of domino logic circuits. The other domino logic circuits used to discriminate the result of proposed circuit are footed domino logic circuit, footless domino logic circuit, high speed domino logic circuit and conditional keeper domino logic circuit. The simulation process here has been done in 65nm CMOS technology using Cadence Virtuoso at 27⁰C operating temperature and 0.8 V supply voltage. In this paper the parameters like delay, average power, no. of transistors and UNG has been calculated and after simulation it is found that the proposed paper gives better output if it is compared with the other circuits.