Power estimations vs. power measurements in Spartan-6 devices

Experimental measurements of power consumption for core logic of a 45-nm Spartan-6 FPGA and the comparison with the values predicted by the power estimation tool are presented. The measurement setup, benchmark suite, and EDA flows utilized to obtain power estimations are described. Several types of multipliers implemented in both LUTs and embedded blocks have been utilized as case-studies. They include versions with different levels of pipelining. In addition, a set of actual circuits obtained from OpenCores is analyzed. Main results of power estimations errors are presented and compared.