Optimization of serial-serial multiplier and implementation of a 4-bit multiplier

In this article partial products algorithm of serial multipliers is presented and different architectures of these kinds of multipliers such as: Successive Addition, Serial-Parallel and Serial-Serial methods are surveyed. With respect to extension capability of pipeline architecture, this circuit is implemented as 4-bit serial-serial multiplier. Some problems have been found and issues were scrutinized. Through improvement in the architecture that is presented as a first method, the problems are eliminated. In following suggested way, it is optimized for speed and area usage of chip. Implementation, simulation and layout have been done by Cadence 6.1.0.243 with TSMC 0.18μm standard cell library. It is found by this improvement that with the total area usage of chip A=0.286nm
²
(result from W∗L) and total power consumption P=3.6mW of power supply, maximum operation frequency is f
max
=700 MHz.