PCI interface implementation using CPLD and FPGA devices

Designing a PCI target or master interface using a CPLD or an FPGA requires special attention to the architectural details of the chip used. This paper reviews typical CPLD and FPGA architectural features relevant to implementations of PCI interfaces. We show different methods for implementing certain aspects of PCI interfaces using a minimal amount of chip resources, while staying compliant with the PCI standard. We discuss specific characteristics of CPLD devices as well as their limitations. Some techniques to make optimum use of CPLDs in terms of density are also discussed.