A memory based architecture for real-time convolution with variable kernels

A new architecture for real-time image convolution with variable kernels is proposed. Due to computation flow transformation and memory-logic integration, we were able to exploit the excessive bandwidth inherent in memory and achieve the fine-grain parallelism of computations. Estimations show that the architecture is suitable for a real-time TV and HDTV picture convolution with very large kernels and can be implemented on a single VLSI chip.