A compact low-power mixed-signal architecture for powerline interference rejection in biopotential analog front ends

This paper proposes a mixed-signal architecture for rejecting strong 50/60 Hz powerline interference (PLI) in biopotential analog front ends (AFEs). The architecture employs a simple least-mean-square algorithm to generate a sinusoidal signal that cancels with the PLI at the AFE's input. Designed and laid out in a 0.18 μm CMOS process, the architecture occupies an area of 0.07 mm². At a clock frequency of 20 kHz for rejecting 50-Hz PLI, simulations show that the architecture consumes a total power of 158 nW, making it attractive for implementations in multi-channel biopotential acquisition systems.