Wave-Pipelined eSFQ Circuits

We have designed and tested energy-efficient single flux quantum (eSFQ) circuits suitable for wave-pipelined architectures. The high energy-efficiency of eSFQ circuits combined with the sequential nature of SFQ logic makes eSFQ especially suitable for energy-efficient variants of highly-pipelined circuits such as modern arithmetic logic units (ALUs), without penalty to the clock speeds available to RSFQ logic. In previous work, we have demonstrated working eSFQ circuits in the form of shift registers, deserializers, counters. Here we expand on this work by introducing a means of moving data through eSFQ circuits without the need for buffering at every step, resembling the wave-pipelined architecture characterizing many large modern logic circuits. Specifically, we present a pipeline-friendly JTL, confluence buffer, and half adder, comprising the core components of many adder architectures. We also show how such an eSFQ full adder naturally lends itself to utilization in a computation pipeline. We report experimental demonstration of circuits manufactured in Hypres's 4.5 kA/cm
²
process.