Managing cache partitioning in multicore processors for certifiable, safety-critical avionics software applications

Multi-core processors (MCPs) present many challenges to developers of certifiable [1], safety-critical software applications. Many of these challenges fall on the system developer/integrator. However, some rely on capabilities the underlying Real-Time Operating System (RTOS) that is used to support these applications. Most importantly, the RTOS must allow application developers to bound and control interference patterns on shared resources (e.g., contention for shared cache). Additionally, it must help minimize the difference between an application's average and worst-case execution times (ACET and WCET, respectively). Without such RTOS capabilities, developers of certifiable, safety-critical applications will find it difficult to achieve the goals of ensuring that the systems they deliver will safely perform their intended functions and maximizing the available CPU bandwidth afforded by MCPs. In this paper, we discuss cache partitioning technology that allows developers to achieve these two goals along with benchmark results that demonstrate its efficacy.