Space-time AER protocol receiver asynchronously controlled on FPGA

Neuromorphic systems have been increasing in size and complexity in recent years, due to the adoption of the Address-Event Representation (AER) as a standard for transmitting signals among chips, and building multi-chip event-based systems. The data amount and speed are keys in address-event receiver devices. Actual receiver designs are based on VLSI and ASIC-FPGA implementation. In this article we present a receiver implemented on reconfigurable devices FPGA, preserving the virtues of useful reconfiguration for design and development inherent of FPGAs. We present the design of the receiver and experimental results, which show the data management capability and speed of reception.