A prototype of mass storage bloch line memory

Since the proposal of vertical Bloch line (VBL) memory, extensive studies on chip architecture as well as investigation on the device functions have been conducted. We already developed a VBL memory using a ring-shaped domain structure as a minor loop, and confirmed minor loop VBL round propagation as well as transfer gate operation and major line bubble propagation, although multi minor loop initialization was not yet examined. In order to demonstrate the feasibility of this device structure, a 0.3 kbit VBL memory with major/minor loop architecture has been developed using partially milled multi ring-shaped domains for minor loops. The chip was fabricated on a 5 um bubble garnet fil m of which composition is (YSmLuCa)₃3 (FeGe)₅0₁₂. Principal device functions such as ring-shaped minor loops, R/W gates and major line are composed of partially milled grooves on the film surface and tri-layer conductor patterns.