P-i-N diode chip temperature extraction method by investigation into maximum recovery current rate di/dt

P-i-N Diode chip temperature is a significant indicator when evaluating the reliability of high power converters. Firstly, the limitation of the forward voltage drop for high power P-i-N diode thermal sensitive electrical parameter (TSEP) is explored. In conventional two-level converter, the commutation is occurred between upper and lower devices. By detailed analysis of the upper P-i-N diode reverse recovery process with lower non-ideal IGBT commutation behavior, the inherent relationship between the maximum recovery current rate did/dt and chip temperature is disclosed. As a result, the maximum did/dt during the recovery period is chosen as better TSEP, which can accurately reflect P-i-N diode chip temperature variation. Fortunately, by monitoring the negative peak voltage on the parasitic inductor between Kelvin emitter and power emitter under different temperatures, the maximum recovery rate did/dt can be readily determined. Finally, a dynamic switching characteristics test platform based on half bridge topology is used to experimentally verify the theoretical analysis. The results show that the dependency between diode chip temperature and maximum recovery did/dt is approximately linear. This leads to a 3-D look-up table that can be used to estimate on-line P-i-N diode chip temperature.