Insulated gate driver for eGaN FET

EPC eGaN transistors have demonstrated performance improvements in comparison with Si MOSFETs ([1], [2] and [3]) but their gate is sensitive to overvoltage (recommended gate source voltage is 5V and the maximum is 6V). In this paper, an efficient insulated and fast gate driver topology is investigated considering parasitic elements. Then, a theoretical and experimental comparison is made. An IC is realized to reduce the gate circuit parasitic elements and its performances are compared with other gate circuit topologies.