Hardware-assisted power estimation for design-stage processors using FPGA emulation

This paper presents the application of an accurate power estimation model for design-stage processors that can be mapped onto an FPGA together with the functional emulation. Based on a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach, the model enables the estimation of application-specific power consumption and energy per task at very early design stages of programmable embedded processors. The extremely short execution time of the emulated power model compared to gate-transfer level (GTL) power simulation allows both hardware and software designers to constantly optimize their implementations for low-power iteratively in different design stages. The power consumption modeling methodology used for this work and necessary considerations for FPGA implementation are described. The presented model is validated against GTL power simulation with respect to execution time and precision by benchmarking for an exemplary embedded RISC processor core, the LEON2. Benchmarking results yield a percentage mean absolute error (%MAE) of less than 9% and normalized root mean square error (NRMSE) of less than 6% while reducing power estimation time from several hours down to a few milliseconds. Finally, a case-study with varying real-world input data sizes has been performed on different software implementations of JPEG encoder and decoder applications and optimized processor core. With software and hardware optimizations applied, required energy per task has been reduced by up to 46% for the JPEG encoder and 39% for the JPEG decoder, demonstrating the advantage of the presented approach.