11.4 Gb/s multiplexer for future broadband communications networks

The authors discuss a 2:1 multiplexer operating from 100 Mb/s to 11.4 Gb/s, which was fabricated using a silicon nitride self-aligned process that features 0.6- mu m-wide arsenic-doped emitters with 4- mu m base-to-base pitch, deep trench isolation, 2- mu m-thick field oxide isolation, polysilicon resistors, and a two-layer TiW-Au metallization. This technology produces transistors with a cutoff frequency (f/sub t/) of 10-15 GHz. The chip measures 0.9*0.8 mm/sup 2/, dissipates 350 mW with a 5-V supply, and operates at the fastest data rate reported to date for a multiplexer in any IC technology.<>