Design and implementation of novel source synchronous interconnection in modern GPU chips

As the architecture of GPU chips evolves to provide higher performance with lower power, new topology of graphics shader engines interconnection to local frame buffers becomes critical. Source synchronous interconnection has been widely adopted in Network-On-Chip (NoC). The SSB bus fabric to transfer data between shader engines and frame buffers adopts more of the globally asynchronous locally synchronous (GALS) design style for a large size GPU chip, in order to deal with the challenge of delivering synchronous high frequencies clocks in the GHz range across full chip. It also reduces the area cost and power consumption on long distance wide width data transfer. In this paper, we present the design structure and physical implementation of a novel source synchronous interconnect network for GALS-style GPU topology. This combines the source synchronous bus lane together with Multiple Data Rate (MDR) structure and much higher transmission clock frequency than shader clock to provide high bandwidth, high speed, low area cost data transmission fabric for GPU chips. We also developed MDR signal bits encoding techniques to reduce the toggle rate of the MDR data nets. With clock gating scheme and MDR signal encoding techniques adapted to the applications, we could further reduce the total power on the SSB transmission fabric.