An FPGA-based development platform for real-time solid state devices

NAND flash-based Solid State Devices (SSD) are widely used in embedded applications because of their low power consumption, high performance, and shock resistant features. However, these devices have non-deterministic response times due to erase-before-write requirements of NAND flash memory. This is a problem for applications that require real-time access to data storage facilities. Recent work has investigated novel RAID-based architectures for highly reliable SSD storage systems, with the host interface, controller, and other facilities such as garbage collectors implemented on an FPGA. The architecture gives high reliability and guarantees of data integrity in a way that protects against the known failure characteristics of flash memory, but at a further expense of timing guarantees. The contribution of this paper is the presentation, design, and analysis of a co-design simulation platform implemented in a PowerPC based FPGA environment that allows us to investigate the timing constraint issues that result from our architecture.