Evaluation of the back-end design overhead for ASIC implementations of large-operand multipliers targeting resource-constrained environments

We investigate different ASIC hardware designs of binary-field multipliers with large operand sizes (>1000 bits). Our architectures target resource-constrained environments such as embedded smart cards or contactless-powered devices and evaluate their applicability. We present several different design strategies based on an iterative Karatsuba, a digit-serial, and a bit-serial multiplier. Based on a cryptographic pairing example application, a total of seven architectures are evaluated in terms of area requirement, speed, and power consumption. Each architecture was subject to a full back-end design flow providing detailed results for synthesis, post-layout, and for an “effective chip” giving realistic design-cost numbers. Providing detailed design flow results, we show that basically all designs exhibit a significant increase in area during their back-end design phase, which can certainly not be considered as negligible.