Architecture of a programmable FIR filter co-processor

This paper presents a new generic architecture to build co-processors dedicated for FIR filtering algorithms, which can implement a set of different filter like symmetric and adaptive filters with or without decimation. Moreover, it manages various types of data (real or complex) and different data accuracies (8 or 16 bits) owing to a specific operative bloc architecture. For instance, a 60.000 equivalent gates co-processor is described that copes with a 512-tap symmetric filter in 8-bit accuracy with a working frequency of 100 MHz (the computation power is 4.8 Gops). So, it could be used as a powerful co-processor for new generation DSPs such as Philips TriMedia and Texas Instruments TMS320C6201 whenever filtering functions are required as in digital communications.