A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS

A single-chip digital polar transmitter integrates an all-digital synthesizer, a PM/AM modulator, and a linearized power amplifier for WCDMA/WLAN. The 1.7~2.5GHz LO signal is generated from an ADPLL together with a ÷1.5 divider to eliminate DCO pulling. A 2-segment ΣΔ phase modulator enhances the PM bandwidth up to 200MHz, and a digital polar amplifier employs AM-replica linearization to eliminate predistortion. The TX measures EVM 4% for a 20MHz-bandwidth 64-QAM while providing a peak output power of 22.1dBm with bit-to-RF efficiency 27.6%.