AHB DDR SDRAM enhanced memory controller

Memory controllers are designed in order to reduce the memory access time which has remained as a memory bottleneck which limits the system performance. This paper shows how to design and implement an Enhanced Memory Controller with high performance AMBA AHB-Lite interface native DDR SDRAM controller. The memory controller features a modular design, fully optimized in terms of resources with pipelined architecture suitable for high-speed operation. All AMBA AHB-Lite protocol transfers are fully supported. Because of AMBA protocol usage it can be easily integrated into any SoC design. Implementation of Enhanced Memory Controller is carried out using VHDL coding and simulation is modeled with MODELSIM. Memory controller is integrated in to a FPGA board in order to carry out the memory transactions